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The NS9210/NS9215 processor family offers a cost-efficient,
small-footprint 32-bit ARM9 solution that combines high
performance, integrated Ethernet networking, strong security,
and unique interface flexibility. It is the ideal choice for a broad
range of applications such as security/access control, medical,
industrial/building automation, transportation and remote
monitoring.
Two independent Flexible Interface Modules (FIMs) with 300
MHz DRPIC1655X processor cores provide a growing list of
application-specific peripheral interface options. The NIST-compliant 256-bit hardware AES accelerator combines state-of-the-art data privacy services with superior performance,
and Digi’s patented dynamic power management addresses the
needs of today’s power budget-conscious designs.
The complete and easy-to-use development kits for NET+OS®
are based on the field-proven ThreadX® Real-Time Operating
System and deliver a true and IPv6-ready turnkey embedded
development solution with the Eclipse-based Digi ESP™ IDE.
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Platform
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NS9210
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NS9215
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General
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Processor
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ARM926EJ-S
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Speed Grades
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75/150 MHz
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Cache
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4 KB I-cache / 4 KB D-cache
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Process
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0.18µ CMOS
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32-bit ARMv5TEJ Instruction Set
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•
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16-bit Thumb Instruction Set
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•
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MMU
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•
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DSP Instruction Extensions
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(Improved divide, Single cycle multiply accumulate)
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ARM Jazelle® Java Accelerator
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•
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Embedded ICE-RT Debug Unit
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•
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JTAG Boundary Scan, BSDL
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•
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Power Management Modes
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•
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AES Accelerator
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Key Length
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128-, 192-, 256-bit
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Cipher Modes
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ECB, CBC, OFB, CTR, CCM
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Hardware Key Expander
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•
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DMA-Enabled
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•
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NIST-Compliant
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•
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FIM (Flexible Interface Module)
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FIMs
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1/2; Availability depending on application-specific use of
external 16-/32-bit memory bus
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2
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Cores
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8-bit DRPIC1655X
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Speed
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Up to 300 MHz (4x bus speed)
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Data Memory (SRAM)
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192 Bytes
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Program Memory (SRAM)
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2 KB
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Interface Options
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SD/SDIO, UART, 1-Wire, CAN, USB device (low-speed), Other; Please contact us for custom interface implementation options
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Power Management
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Dynamic Clock Scaling (patent pending)
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Full, /2, /4, /8, /16 speeds, with hardware clock scale control (wake-up events)
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Low-Power Sleep Modes
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•
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Configurable Wake-Up Conditions
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External IRQ, I2
C, SPI, UART, Ethernet
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External IRQ, I2
C, SPI, UART, Ethernet, RTC
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Disabling of Unused System Modules
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•
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Memory Controller
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Glue-less Interface
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(SDRAM, SRAM, Buffered DIMM, EEPROM, Flash)
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Self-Refresh (Sleep Mode)
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•
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Dynamic/Static Memory Chip Selects
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Selection of 5
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4/4
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Wait States Per Memory Chip Select
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0-32
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Static Memory Controller Extended Waits (EW)
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Up to 16,368
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Automatic Dynamic Bus Sizing
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•
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Burst Support
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8-transfer, with automatic data width adjustment
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External DMA Channels
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2
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System Bus DMA
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High-Speed Rotating AHB arbiter
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16 channels
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Deterministic Bus Bandwidth Allocation
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•
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Multiple Bus Masters
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Ethernet Tx/Rx, I/O Hub, Ext DMA, ARM core
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External DMA
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Independent DMA Channels
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2
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Transfer Modes
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External peripherals, External memory, AHB peripherals
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AES DMA Support
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•
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AHB Master
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•
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I/O Hub
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Low Latency
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•
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DMA
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8 channels
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DMA or Direct Access Mode
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UART, SPI, FIM
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UART, SPI, ADC, FIM
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Direct Access Mode Only
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I2C
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I2C, RTC
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AHB Master
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•
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External Interrupts
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External Programmable Interrupts
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4
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Advanced Vectored Interrupt Controller
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Two-Tier Priority
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(FIRQ/IRQ)
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Low-Latency FIRQ
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•
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Interrupt Sources
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32
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Ethernet MAC
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Data Rates
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10 / 100 Mbit/s
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Duplex
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Full and Half
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PHY Interface
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MII
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Address Filtering
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Station, Broadcast, Multicast
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FIFO
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Features
- High-performance 150 MHz ARM926EJ-S core
- 10/100 Mbit Ethernet MAC integration
- On-chip hardware AES accelerator
- Software-configurable I/O flexibility through FIMs
- Power management modes with dynamic clock scaling
- Rich set of integrated peripheral interfaces
- Complete and royalty-free NET+OS development
platform for network-enabled embedded devices
- Upgrade path to ARM9 core performance for existing
NS7520 designs through pin-compatible NS9210
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